SRAM cells are one of the most popular ways to store data in electronic systems. Further, embedded SRAM cells are a vital building block in integrated circuits. SRAM cells are typically preferred because of higher speed, robust design, and ease of integration. However, SRAM cells, in general, occupy a significantly large portion of a chip's die area, making it an important block in terms of yield, reliability and power consumption. With increasing demand for highly integrated System on Chip (SoC) design, improving various aspects of embedded SRAM cells has received significant interest.
Specifically, nano-metric semiconductor technologies are becoming highly sensitive to transients induced by ionizing radiation consisting of energetic cosmic neutrons and alpha particles. These particles generate a large number of electron hole pairs, which may be collected by sensitive nodes resulting in data upset, also known as soft errors (SE). Accordingly, a number of solutions have been proposed to improve the robustness of the SRAM cell.
For example, referring to FIG. 2, a schematic diagram of an SRAM cell having improved robustness to radiation induced soft errors is shown. In the proposed solution, the SRAM includes a coupling capacitor. The coupling capacitor significantly increases the critical charge (Qc), which is the minimum charge required to cause an soft error. However, adding a large, area efficient coupling capacitor requires a special semiconductor manufacturing process. Therefore the proposed SRAM cell is not easily integrated with common Complementary metal-oxide-semiconductor (CMOS) digital circuits. As a consequence, for Application Specific Integrated Circuits (ASICs) where embedded SRAM cells are widely realized using standard CMOS process, it is rather difficult to implement.
Referring to FIG. 3, a schematic diagram of an alternate SRAM cell having improved robustness to soft errors is shown. In the proposed solution, a soft error robust data latch is implemented. The latch is immune to single node upsets. However, implementing the solution as an SRAM cell with differential ports requires additional transistors making it expensive.
Technology scaling is making SRAM cells susceptible to radiation induced soft errors. Therefore, building a soft error robust SRAM cell is becoming a high priority. Further, it is desirable to improve the cell immunity against soft errors while limiting the number of extra transistors. Reducing the number of transistors allows the SRAM cell to occupy less space, which permits higher cell density.